Automated stored pattern functional testing affords a critical step in the production of integrated circuit (IC) devices to provide parametric and operational characterization of the devices. An automatic test equipment system includes test circuitry that is connected to a control computer. The control computer provides a user interface that accepts and stores functional test pattern data for activating the test circuitry to provide stimulus signals to a device-under-test and receives the response signals from the device-under-test. The response signals are evaluated to determine the parametric and operational characterization of the integrated circuit devices.
The device-under-test (DUT) is mounted on a device interface board or DIB, which provides the physical interface from/to the pin electronics. The pin electronics circuitry is the electrical interface that provides/receives the electrical test stimulus/response signals to/from the device-under-test via the DIB. The test stimulus signals from the test circuitry are supplied through pin electronics to the device-under-test via the DIB. The test response signals from the device-under-test are transferred through DIB to the pin electronics and on to the test circuitry. The test stimulus signals and the test response signals are correlated by the test circuitry to determine whether the device-under-test has passed or failed the test.
The stimulus signals generated by the test circuitry include data signals and clock signals to synchronize the stimulus input. The effectiveness of the test depends on the accurate placement of these signals relative to one another. For example, several different signals, such as, clock, data, and enable signals are coordinated and triggered at appropriate times to ensure that meaningful data is acquired during the test process. Inaccuracy of clock and data signal edge placement will result in false test results. As the operating speed of devices to be tested increases, the margins of error for edge placement accuracy decreases.
A system-on-a-chip (SOC) provides multiple digital and analog integrated circuit functions incorporated on the same semiconductor substrate. An example of an SOC is a cellular telephone that incorporates not only cellular telephone receiving, processing, and transmitting functions, but also photographic and video processing functions, audio digital signal processing and semiconductor memory circuits. Presently, in most SOC testing, the individual functions of an SOC are tested separately in multiple testing methods, such as by SCAN testing, Built-In-Self-Test (BIST), and functional testing. System Level Test typically employs custom circuitry and is generally only used for high average selling price low mix devices, such as microprocessors. A final system level test may be implemented on customized test apparatus created specifically for the testing of specific SOC devices such as microprocessors. Although it would be desirable to perform a System Level Test for other SOC devices, building custom functional test apparatuses for low average selling price SOCs is not cost effective.
A difficulty in testing SOCs with automatic test circuitry is that the parametric and individual functional testing with the automatic test circuitry is a deterministic test operation. The test stimulus signals are applied with certain timing and structure, and the test response signals are expected to have a particular timing and structure. If the test response signals do not match the expected timing and structure for the given parameters, the SOC device-under-test is determined to have failed. The functions of the SOC device may operate with differing timing and clocking specifications and may in fact operate asynchronously. An SOC device may be operational when the response test signals indicate otherwise, when the asynchronicity of the communicating functions cause the test response signals to appear incorrect.
There have been attempts within present automatic test equipment systems to simulate the operating conditions of an SOC device-under-test. Because of the nondeterministic function of the asynchronous communication between circuit functions, the normal operating environment of the functions can not be accurately recreated for the SOC device-under-test. Present automatic test equipment environments lack the ability to easily and accurately provide the nondeterministic electrical and timing conditions of the normal operating environment of the SOC device-under-test. This lack of the nondeterministic electrical and timing conditions within automatic test equipment systems, further do not measure the margin of error for an SOC device-under-test with regard to its tolerance under varying operational conditions that may be present in its normal operational environment.
Therefore, what is needed is an automatic test equipment system capable of providing deterministic and nondeterministic test stimulus signals. The nondeterministic test stimulus signals provide the electrical and timing protocol of the normal operating environment of the device-under-test such that the automatic test equipment system responds to test response signals of the device-under-test as though the device-under-test is operating in its normal environment.